From 3880306f431272c74ab63a49ee6aa566884bdd9f Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Wed, 28 Oct 2026 16:00:28 -0400 Subject: [PATCH 1/2] stm32wba: set HPRE5 to divide-by-4 for AHB5 HPRE5 value 0b101 divides by 3 per RM0493, which put HCLK5 at 33.3 MHz with a 100 MHz SYSCLK, above the 32 MHz AHB5 limit. Use 0b110 (divide-by-4) for 25 MHz. --- hal/boards/stm32wba55cg_nucleo/wolfHAL_board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hal/boards/stm32wba55cg_nucleo/wolfHAL_board.c b/hal/boards/stm32wba55cg_nucleo/wolfHAL_board.c index 18ed99c0f5..9b152cf7f6 100644 --- a/hal/boards/stm32wba55cg_nucleo/wolfHAL_board.c +++ b/hal/boards/stm32wba55cg_nucleo/wolfHAL_board.c @@ -80,8 +80,8 @@ static void pll_clock_on(void) whal_Stm32wba_Rcc_EnablePeriphClk(&g_flashClock); whal_Stm32wba_Flash_Ext_SetLatency(BOARD_FLASH_DEV, 3); - /* AHB5 max 32 MHz: prescale 100 MHz / 4 = 25 MHz (0b101 = div 4). */ - whal_Stm32wba_Rcc_SetHpre5(5); + /* AHB5 max 32 MHz: prescale 100 MHz / 4 = 25 MHz (0b110 = div 4). */ + whal_Stm32wba_Rcc_SetHpre5(6); whal_Stm32wba_Rcc_EnableOsc( &(whal_Stm32wba_Rcc_OscCfg){WHAL_STM32WBA_RCC_HSE32_CFG}); From 1deda6241ec7db98ddf5ccfd769b0b7855ae4202 Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Thu, 29 Oct 2026 10:03:17 -0400 Subject: [PATCH 2/2] Update wolfHAL submodule to latest commit --- lib/wolfHAL | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/wolfHAL b/lib/wolfHAL index 63cedc8e11..a1cfc5cacf 160000 --- a/lib/wolfHAL +++ b/lib/wolfHAL @@ -1 +1 @@ -Subproject commit 63cedc8e11bbecd116446732efb23d71ed8ce7db +Subproject commit a1cfc5cacffe2397daac5de25359868b961112dc