ru551n · Oct 21, 2026 · Oct 21, 2026
diff --git a/pyproject.toml b/pyproject.toml
@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "vunit-python-bridge"
-version = "0.2.0"
+version = "0.3.0"
 description = "A VUnit package making Python callable from VHDL."
 urls = {homepage = "https://github.com/VUnit/vunit-python-bridge"}
 readme = "README.md"

diff --git a/release_notes/0.3.0.md b/release_notes/0.3.0.md
@@ -0,0 +1,6 @@
+
+## Features
+
+- The `std_ulogic_vector`, `signed` and `unsigned` results of `eval` and `call` are also functions taking the width like `to_unsigned`, as a length or as `size_res`: `byte := call_unsigned("model.pop", byte'length)`. (#15)
+- Python objects: `python_object_t` is an instance of a Python class owned by VHDL, whose methods VHDL calls. See "Python objects" in the user guide. (#15)
+- Riviera-PRO is a supported simulator. (#21)
diff --git a/release_notes/news.d/15.feature.2.md b/release_notes/news.d/15.feature.2.md
diff --git a/release_notes/news.d/15.feature.md b/release_notes/news.d/15.feature.md
diff --git a/release_notes/news.d/21.feature.md b/release_notes/news.d/21.feature.md