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drm/vc4: hdmi: write SCDC TMDS_Bit_Clock_Ratio before the TMDS clock starts - #7695
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…starts HDMI 2.0 requires a source to suspend the TMDS clock, write the TMDS_Bit_Clock_Ratio bit in the sink's SCDC registers, wait at least 1 ms and only then resume the clock. vc4 does the opposite: the PHY starts at the new rate first, and the SCDC bits are written tens of milliseconds later from the post-enable step. On disable the bits are cleared while the clock is still running. Some sinks sample the bit only when the clock appears. One HDMI 2.0 sink we tested then sets up its receiver for a 1/10 clock and never recovers: a Raspberry Pi 5 at 3840x2160@60 shows no picture, while 1080p60 and 4K30 work and other sources work at 4K60 on the same sink. Writing the bit by hand before enabling the output makes the same mode lock every time. Fixes: c85695a ("drm/vc4: hdmi: Enable the scrambler") Assisted-by: LLM Signed-off-by: Lucas Tanure <lucas.tanure@neat.no>
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This looks plausible to me. As we largely use the upstream vc4 driver, it would be best to get this fixed at source. |
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HDMI 2.0 requires a source to suspend the TMDS clock, write the TMDS_Bit_Clock_Ratio bit in the sink's SCDC registers, wait at least 1 ms and only then resume the clock. vc4 does the opposite: the PHY starts at the new rate first, and the SCDC bits are written tens of milliseconds later from the post-enable step. On disable the bits are cleared while the clock is still running.
Some sinks sample the bit only when the clock appears. One HDMI 2.0 sink we tested then sets up its receiver for a 1/10 clock and never recovers: a Raspberry Pi 5 at 3840x2160@60 shows no picture, while 1080p60 and 4K30 work and other sources work at 4K60 on the same sink. Writing the bit by hand before enabling the output makes the same mode lock every time.
Fixes: c85695a ("drm/vc4: hdmi: Enable the scrambler")
Assisted-by: LLM
Signed-off-by: Lucas Tanure lucas.tanure@neat.no