Add wolfBoot target for Infineon PSOC Edge E8

.github/workflows/test-configs.yml

@@ -1054,6 +1054,39 @@ jobs:
       arch: arm
       config-file: ./config/examples/stm32c5.config
 
+  psoc_e8_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/psoc_e8_ai.config
+
+  psoc_e8_wolfcrypt_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/psoc_e8_ai.config
+      make-args: WOLFCRYPT_TEST=1 WOLFCRYPT_BENCHMARK=1
+
+  psoc_e8_tz_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/psoc_e8_ai-tz.config
+
+  psoc_e8_tz_wolfhsm_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/psoc_e8_ai-tz-wolfhsm.config
+
+  # wolfBoot linked into RRAM, partitions still in QSPI.
+  psoc_e8_rram_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/psoc_e8_ai.config
+      make-args: PSOC_E8_BOOT_RRAM=1
+
   psoc_c3_test:
     uses: ./.github/workflows/test-build.yml
     with:

.gitignore

@@ -144,6 +144,8 @@ tools/unit-tests/unit-aes256
 tools/unit-tests/unit-chacha20
 tools/unit-tests/unit-delta
 tools/unit-tests/unit-psoc-c3-divider
+tools/unit-tests/unit-psoc-e8-tz
+tools/unit-tests/unit-psoc-e8-flash
 tools/unit-tests/unit-disk
 tools/unit-tests/unit-fs-probe
 tools/unit-tests/unit-fat32

Makefile

@@ -408,6 +408,11 @@ ifeq ($(TARGET),mcxn)
 endif
 endif # TZEN=1
 
+ifeq ($(TARGET),psoc_e8)
+	# wolfBoot is programmed with its boot header, not as a contiguous image
+    MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
+endif
+
 ifeq ($(TARGET),pic32cz)
     MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
 endif

arch.mk

@@ -758,6 +758,68 @@ ifeq ($(ARCH),ARM)
     CFLAGS+=-DPSOC_C3_I2C_HSIOM_SEL=$(PSOC_C3_I2C_HSIOM_SEL)
     CFLAGS+=-DPSOC_C3_I2C_HZ=$(PSOC_C3_I2C_HZ)
   endif
+  ifeq ($(TARGET),psoc_e8)
+    CORTEX_M33=1
+    CFLAGS+=-Ihal
+    # Extended boot runs the first CM33 image in place, after a 0x400 boot
+    # header: from QSPI by default, or from RRAM with PSOC_E8_BOOT_RRAM=1
+    # (needs the boot policy reprovisioned). ARCH_FLASH_OFFSET is the slot,
+    # which also holds the header's 0x28-byte SHA-256 trailer after wolfBoot.
+    PSOC_E8_BOOT_RRAM?=0
+    ifeq ($(PSOC_E8_BOOT_RRAM),1)
+      PSOC_E8_RRAM_SLOT_SIZE?=0x20000
+      ARCH_FLASH_OFFSET=0x12011000
+      WOLFBOOT_ORIGIN=0x12011400
+      BOOTLOADER_PARTITION_SIZE=$$(( $(PSOC_E8_RRAM_SLOT_SIZE) - 0x400 - 0x40))
+    else
+      ARCH_FLASH_OFFSET=0x18100000
+      WOLFBOOT_ORIGIN=0x18100400
+      # The boot partition is in the Non-secure alias with TZEN=1.
+      BOOTLOADER_PARTITION_SIZE=$$(( ($(WOLFBOOT_PARTITION_BOOT_ADDRESS) | 0x10000000) - $(WOLFBOOT_ORIGIN) - 0x40))
+    endif
+    ifeq ($(TZEN),1)
+      LSCRIPT_IN=hal/$(TARGET)-tz.ld
+      OBJS+=hal/psoc_e8_tz.o
+      # wolfHSM NVM in the RRAM user area, Secure.
+      WOLFBOOT_KEYVAULT_ADDRESS?=0x32040000
+      WOLFBOOT_KEYVAULT_SIZE?=0x10000
+    else
+      LSCRIPT_IN=hal/$(TARGET).ld
+    endif
+    # Board wiring, defaulted for KIT_PSE84_AI.
+    PSOC_E8_UART_SCB?=2
+    PSOC_E8_UART_PORT?=6
+    PSOC_E8_UART_RX_PIN?=5
+    PSOC_E8_UART_TX_PIN?=7
+    PSOC_E8_UART_HSIOM_SEL?=20
+    PSOC_E8_UART_PCLK_GR?=1
+    PSOC_E8_UART_PCLK_IDX?=1
+    PSOC_E8_PCLK_HZ?=100000000
+    PSOC_E8_QSPI_SECTOR_SIZE?=0x40000
+    PSOC_E8_QSPI_SIZE?=0x4000000
+    PSOC_E8_CPU_HZ?=200000000
+    CFLAGS+=-DPSOC_E8_UART_SCB=$(PSOC_E8_UART_SCB)
+    CFLAGS+=-DPSOC_E8_UART_PORT=$(PSOC_E8_UART_PORT)
+    CFLAGS+=-DPSOC_E8_UART_RX_PIN=$(PSOC_E8_UART_RX_PIN)
+    CFLAGS+=-DPSOC_E8_UART_TX_PIN=$(PSOC_E8_UART_TX_PIN)
+    CFLAGS+=-DPSOC_E8_UART_HSIOM_SEL=$(PSOC_E8_UART_HSIOM_SEL)
+    CFLAGS+=-DPSOC_E8_UART_PCLK_GR=$(PSOC_E8_UART_PCLK_GR)
+    CFLAGS+=-DPSOC_E8_UART_PCLK_IDX=$(PSOC_E8_UART_PCLK_IDX)
+    CFLAGS+=-DPSOC_E8_PCLK_HZ=$(PSOC_E8_PCLK_HZ)
+    CFLAGS+=-DPSOC_E8_QSPI_SECTOR_SIZE=$(PSOC_E8_QSPI_SECTOR_SIZE)
+    # QSPI through src/qspi_flash.c, single-line with 4-byte opcodes. The
+    # driver runs from RAM because wolfBoot executes from the same device; it
+    # is used directly, not as EXT_FLASH, so the partitions stay in place.
+    OBJS+=src/qspi_flash.o
+    CFLAGS+=-DQSPI_FLASH -DQSPI_FLASH_RAM_CODE -DQSPI_ADDR_SZ=4
+    CFLAGS+=-DQSPI_NO_4BYTE_MODE
+    CFLAGS+=-DQSPI_DATA_MODE=QSPI_DATA_MODE_SPI
+    CFLAGS+=-DPAGE_PROG_CMD=0x12 -DSEC_ERASE_CMD=0xDC
+    CFLAGS+=-DFLASH_DEVICE_SIZE=$(PSOC_E8_QSPI_SIZE)
+    CFLAGS+=-DSPI_FLASH_SECTOR_SIZE=$(PSOC_E8_QSPI_SECTOR_SIZE)
+    CFLAGS+=-DQSPI_FLASH_READY_TRIES=4000000
+    CFLAGS+=-DPSOC_E8_CPU_HZ=$(PSOC_E8_CPU_HZ)
+  endif
   ifeq ($(TARGET),m2354)
     CORTEX_M23=1
     CFLAGS+=-Ihal

config/examples/psoc_e8_ai-tz-wolfhsm.config

@@ -0,0 +1,50 @@
+ARCH?=ARM
+TARGET?=psoc_e8
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=0
+VTOR?=1
+CORTEX_M33?=1
+TZEN?=1
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+# The QSPI NOR rejects a second program into a 16-byte ECC unit.
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=1
+DUALBANK_SWAP?=0
+DEBUG_UART=1
+# Keeps the application vector table 1 KB aligned.
+IMAGE_HEADER_SIZE?=1024
+
+# KIT_PSE84_AI with TrustZone and a wolfHSM server in the Secure world. The
+# Non-secure application is the wolfHSM client, over the NSC transport, and
+# uses SRAM1 (0x24080000). 64 MB QSPI NOR, 256 KB sectors; the boot partition
+# is in the Non-secure code-bus alias, the rest in the Secure one. Erase the
+# key store once with psoc_e8_flash.sh --erase-keyvault.
+#
+#   0x32040000 - 0x3204FFFF  RRAM wolfHSM NVM (WOLFBOOT_KEYVAULT_*)
+#   0x34058000 - 0x3407FFFF  SRAM0 top, Secure wolfHSM heap
+#   0x18100000 - 0x1813BFFF  wolfBoot slot: 0x400 boot header + wolfBoot
+#   0x1813C000 - 0x1813FFFF  NSC gateway veneers
+#   0x08140000 - 0x0823FFFF  BOOT              (1 MB, Non-secure)
+#   0x18240000 - 0x1833FFFF  UPDATE            (1 MB)
+#   0x18340000 - 0x1837FFFF  SWAP              (one sector)
+#
+# Board wiring: PSOC_E8_* make options in arch.mk, see docs/Targets.md.
+WOLFBOOT_SECTOR_SIZE?=0x40000
+WOLFBOOT_PARTITION_SIZE?=0x100000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08140000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x18240000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x18340000
+WOLFBOOT_NSC_ADDRESS?=0x1813C000
+WOLFBOOT_NSC_SIZE?=0x4000
+WOLFCRYPT_TZ=1
+WOLFCRYPT_TZ_WOLFHSM=1
+WOLFBOOT_KEYVAULT_ADDRESS?=0x32040000
+WOLFBOOT_KEYVAULT_SIZE?=0x10000

config/examples/psoc_e8_ai-tz.config

@@ -0,0 +1,43 @@
+ARCH?=ARM
+TARGET?=psoc_e8
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=0
+VTOR?=1
+CORTEX_M33?=1
+TZEN?=1
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+# The QSPI NOR rejects a second program into a 16-byte ECC unit.
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=1
+DUALBANK_SWAP?=0
+DEBUG_UART=1
+# Keeps the application vector table 1 KB aligned.
+IMAGE_HEADER_SIZE?=1024
+
+# KIT_PSE84_AI with TrustZone: wolfBoot Secure, the application Non-secure.
+# 64 MB QSPI NOR, 256 KB sectors. The boot partition is in the Non-secure
+# code-bus alias, the rest in the Secure one. The application uses SRAM1
+# (0x24080000) and prints through a Secure console gateway.
+#
+#   0x18100000 - 0x1813BFFF  wolfBoot slot: 0x400 boot header + wolfBoot
+#   0x1813C000 - 0x1813FFFF  NSC gateway veneers
+#   0x08140000 - 0x0823FFFF  BOOT              (1 MB, Non-secure)
+#   0x18240000 - 0x1833FFFF  UPDATE            (1 MB)
+#   0x18340000 - 0x1837FFFF  SWAP              (one sector)
+#
+# Board wiring: PSOC_E8_* make options in arch.mk, see docs/Targets.md.
+WOLFBOOT_SECTOR_SIZE?=0x40000
+WOLFBOOT_PARTITION_SIZE?=0x100000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08140000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x18240000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x18340000
+WOLFBOOT_NSC_ADDRESS?=0x1813C000
+WOLFBOOT_NSC_SIZE?=0x4000

config/examples/psoc_e8_ai.config

@@ -0,0 +1,37 @@
+ARCH?=ARM
+TARGET?=psoc_e8
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=0
+VTOR?=1
+CORTEX_M33?=1
+TZEN?=0
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+# The QSPI NOR rejects a second program into a 16-byte ECC unit.
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=1
+DUALBANK_SWAP?=0
+DEBUG_UART=1
+# Keeps the application vector table 1 KB aligned.
+IMAGE_HEADER_SIZE?=1024
+
+# KIT_PSE84_AI: 64 MB QSPI NOR, 256 KB sectors, Secure code-bus alias.
+#
+#   0x18100000 - 0x1813FFFF  wolfBoot slot: 0x400 boot header + wolfBoot
+#   0x18140000 - 0x1823FFFF  BOOT              (1 MB)
+#   0x18240000 - 0x1833FFFF  UPDATE            (1 MB)
+#   0x18340000 - 0x1837FFFF  SWAP              (one sector)
+#
+# Board wiring: PSOC_E8_* make options in arch.mk, see docs/Targets.md.
+WOLFBOOT_SECTOR_SIZE?=0x40000
+WOLFBOOT_PARTITION_SIZE?=0x100000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x18140000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x18240000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x18340000

docs/Targets.md

@@ -11,6 +11,7 @@ This README describes configuration of supported targets.
 * [Cortex-A72 / Raspberry Pi Compute Module 4](#cortex-a72--raspberry-pi-compute-module-4-bcm2711)
 * [Cypress PSoC-6](#cypress-psoc-6)
 * [Infineon PSOC Control C3](#infineon-psoc-control-c3)
+* [Infineon PSOC Edge E8](#infineon-psoc-edge-e8)
 * [Infineon AURIX TC3xx](#infineon-aurix-tc3xx)
 * [Infineon AURIX TC4xx](#infineon-aurix-tc4xx)
 * [Intel x86-64 Intel FSP](#intel-x86_64-with-intel-fsp-support)
@@ -10026,6 +10027,99 @@ A TPM that offers both buses latches its choice from a strap while its own reset
 
 Every FIFO and bus wait in both drivers is bounded, so a device that is absent or unpowered makes `wolfBoot_tpm2_init()` report a failure rather than wedging the bootloader in a spin loop.
 
+## Infineon PSOC Edge E8
+
+The Infineon PSOC Edge E8 family (PSE8x, CAT1D) pairs a Cortex-M33 with TrustZone and a Cortex-M55 behind a Secure Enclave, which runs the boot ROM and Infineon's extended boot. wolfBoot runs on the CM33 in the Secure state as the first image extended boot launches. The port is bare metal and needs no Peripheral Driver Library or BSP. Board differences are make options, and `config/examples/psoc_e8_ai.config` describes KIT_PSE84_AI.
+
+Verified on KIT_PSE84_AI (PSE846GPS2DBZC4A): boot from QSPI under the factory extended boot, ECC256 verification and handoff, A/B update with confirmation, resumption of an update interrupted mid-swap, RRAM write and erase, and the wolfCrypt test and benchmark. With TrustZone, the Non-secure application booting from the Secure wolfBoot, the A/B update through the gateway calls, Secure-memory isolation and the wolfHSM client test suite against the Secure server were verified on the same board. Booting from RRAM (`PSOC_E8_BOOT_RRAM=1`) is build-tested only. The CM55 is not started.
+
+### Boot chain and memory
+
+Extended boot runs the first CM33 image in place from QSPI at `0x60100000`. It requires a 0x400-byte header and a trailing SHA-256 of header and image (an unsigned, MCUboot-compatible format), which `tools/scripts/psoc_e8/psoc_e8_boot_header.py` adds to `wolfboot.bin`.
+
+Each memory has four aliases, Secure/Non-secure by code/system bus. wolfBoot links at `0x18100400`; the layout below is the non-TrustZone configuration and uses the Secure code-bus QSPI alias:
+
+```
+RRAM    0x02000000 NS code   0x12000000 S code   0x22000000 NS sys   0x32000000 S sys
+QSPI    0x08000000 NS code   0x18000000 S code   0x60000000 NS sys   0x70000000 S sys
+
+0x18100000 - 0x1813FFFF  wolfBoot slot (boot header + wolfBoot)
+0x18140000 - 0x1823FFFF  BOOT partition      (1 MB)
+0x18240000 - 0x1833FFFF  UPDATE partition    (1 MB)
+0x18340000 - 0x1837FFFF  SWAP sector         (256 KB)
+```
+
+`IMAGE_HEADER_SIZE=1024` keeps the application vector table on the 1 KB boundary the CM33 requires.
+
+### QSPI flash
+
+QSPI is programmed through the generic `src/qspi_flash.c` driver, without `EXT_FLASH`, so the partitions stay in place for execute-in-place. The HAL supplies its `qspi_transfer()` over the SMIF MMIO command interface, using the device extended boot configured, and the driver is built with `QSPI_FLASH_RAM_CODE`, dedicated 4-byte opcodes and `QSPI_NO_4BYTE_MODE` so the part stays in the address mode extended boot expects. Writes run from RAM with interrupts masked, stage each page in RAM (the source is often QSPI itself), and invalidate the SMIF and CM33 caches afterwards. The test application runs from the QSPI it programs, so its flash path is also placed in RAM.
+
+The NOR keeps ECC over 16-byte units and rejects a second program into a unit, so the config sets `NVM_FLASH_WRITEONCE=1`. With 256 KB sectors this costs a sector-sized RAM buffer. A rejected program leaves the part busy across a warm reset, where extended boot can no longer read it, so the HAL clears the failure flags when it sees them.
+
+### Build options
+
+wolfBoot does not change the clocks extended boot sets. The console is SCB2 on P6.5/P6.7, the KitProg3 COM port, at 115200 baud.
+
+| Option | Default | Purpose |
+| --- | --- | --- |
+| `PSOC_E8_UART_SCB` | 2 | console SCB instance |
+| `PSOC_E8_UART_PORT` / `_RX_PIN` / `_TX_PIN` | 6 / 5 / 7 | console pins |
+| `PSOC_E8_UART_HSIOM_SEL` | 20 | HSIOM selector for the UART |
+| `PSOC_E8_UART_PCLK_GR` / `_IDX` | 1 / 1 | console peripheral clock group and index |
+| `PSOC_E8_PCLK_HZ` | 100000000 | CLK_HF10, feeding that group |
+| `PSOC_E8_CPU_HZ` | 200000000 | CLK_HF0, test-app benchmark time base |
+| `PSOC_E8_QSPI_SECTOR_SIZE` | 0x40000 | QSPI erase sector |
+| `PSOC_E8_QSPI_SIZE` | 0x4000000 | QSPI device size |
+| `PSOC_E8_BOOT_RRAM` | 0 | link wolfBoot into RRAM instead of QSPI |
+| `PSOC_E8_RRAM_SLOT_SIZE` | 0x20000 | RRAM slot with `PSOC_E8_BOOT_RRAM=1` |
+
+### Building and flashing
+
+```sh
+cp config/examples/psoc_e8_ai.config .config
+make clean && make
+tools/scripts/psoc_e8/psoc_e8_flash.sh
+```
+
+The script adds the boot header to `wolfboot.bin` and programs it and `test-app/image_v1_signed.bin` over the KitProg3, with the ModusToolbox Programming Tools OpenOCD (`MTB_PROGTOOLS`, default `/opt/Tools/ModusToolboxProgtools-1.6`). Set `KITPROG_SERIAL` if several probes are attached. This replaces the factory CM33 image, so read QSPI back first to keep the stock demo.
+
+To test an update, sign v2 and program it into UPDATE. The v1 application triggers the update, and v2 confirms itself:
+
+```sh
+IMAGE_HEADER_SIZE=1024 ./tools/keytools/sign --ecc256 --sha256 \
+    test-app/image.bin wolfboot_signing_private_key.der 2
+tools/scripts/psoc_e8/psoc_e8_flash.sh --update test-app/image_v2_signed.bin
+```
+
+`make WOLFCRYPT_TEST=1 WOLFCRYPT_BENCHMARK=1` adds the software wolfCrypt test and benchmark to the test application. Its RNG seed is deterministic and only for testing.
+
+### TrustZone and wolfHSM
+
+`config/examples/psoc_e8_ai-tz.config` runs wolfBoot in the Secure state and the application Non-secure. `config/examples/psoc_e8_ai-tz-wolfhsm.config` adds a wolfHSM server in the Secure world (`WOLFCRYPT_TZ_WOLFHSM=1`), which the Non-secure application reaches as a wolfHSM client through one gateway call, as on STM32H5 (see [wolfHSM.md](wolfHSM.md)).
+
+```
+0x18100000 - 0x1813BFFF  wolfBoot slot (Secure)
+0x1813C000 - 0x1813FFFF  NSC gateway veneers
+0x08140000 - 0x0823FFFF  BOOT partition, Non-secure alias
+0x18240000 - 0x1837FFFF  UPDATE and SWAP, Secure
+0x24080000 - 0x240FFFFF  SRAM1, Non-secure application RAM
+0x34058000 - 0x3407FFFF  SRAM0 top, Secure wolfHSM heap
+0x32040000 - 0x3204FFFF  RRAM, wolfHSM NVM (WOLFBOOT_KEYVAULT_*)
+```
+
+The CM33 runs both worlds in protection context 2, so `hal_init()` grants that context Non-secure access to the boot partition in the SMIF memory protection controller and to SRAM1 in its controller, and adds SAU regions for those and the gateway. wolfBoot then reads and verifies the boot partition through its Non-secure alias. Peripherals stay Secure: the application updates through the `wolfBoot_nsc_*` calls and prints through a console gateway. The crypto block's TRNG, with both health monitors running, seeds the Secure DRBG.
+
+Fresh RRAM reads as zero, which the wolfHSM NVM does not accept as empty, so program a board once with `--erase-keyvault`, which fills the key store with 0xFF and destroys anything stored there:
+
+```sh
+tools/scripts/psoc_e8/psoc_e8_flash.sh --erase-keyvault
+```
+
+### Booting from RRAM
+
+`PSOC_E8_BOOT_RRAM=1` links wolfBoot at `0x12011400` in the RRAM user area, keeping the partitions in QSPI. Extended boot only launches it once the boot policy is reprovisioned with Infineon's Edge Protect Tools, which this port does not automate. RRAM is written in 16-byte blocks through the RRAMC indirect-write action, under the IPC and PC_LOCK locks. It has no erase, so `hal_flash_erase()` fills the range with 0xFF to read like erased NOR.
+
 ## Infineon AURIX TC3xx
 
 wolfBoot supports the Infineon AURIX TC3xx family and includes a demo application for the TC375 AURIX LiteKit-V2. It can be configured to run on either the TriCore application cores or the HSM core.

docs/wolfHSM.md

@@ -23,6 +23,7 @@ wolfBoot supports using wolfHSM on the following platforms:
 - AURIX TC3xx (shared memory transport)
 - Microchip PIC32CZ CA9x (shared memory transport)
 - STM32H5 TrustZone (the secure-side wolfBoot hosts a wolfHSM server and exposes it to the non-secure application through a single NSC veneer; see [STM32H5 TrustZone Engine](#stm32h5-trustzone-engine) below)
+- Infineon PSOC Edge E8 TrustZone (the same engine, with the NVM in RRAM; see the PSOC Edge E8 section of [Targets.md](Targets.md))
 
 Details on configuring wolfBoot to use wolfHSM on each of these platforms can be found in the wolfBoot (and wolfHSM) documentation specific to that target, with the exception of the simulator, which is documented here. The remainder of this document focuses on the generic wolfHSM-related configuration options.
 
@@ -315,4 +316,6 @@ The default build prints a final `WOLFHSM_TZ_TEST_PASS` UART line on success. Th
 
 ### Notes
 
+The same engine runs on Infineon PSOC Edge E8 (`config/examples/psoc_e8_ai-tz-wolfhsm.config`), with the NVM in RRAM through the same flash adapter.
+
 The wolfHSM NVM lives in the existing `FLASH_KEYVAULT` region (112 KiB at `0x0C040000`) shared with the other STM32H5 TrustZone engines. The flash adapter (`src/wolfhsm_flash_hal.c`) caches the affected sector, modifies it, and rewrites the whole 8 KiB sector in one erase + program cycle, mirroring `psa_store.c` / `pkcs11_store.c`. This satisfies the H5 quad-word ECC rule that each 16-byte unit may be programmed exactly once between erases, which wolfHSM's 8-byte-unit writes would otherwise violate.