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stm32wba: set HPRE5 to divide-by-4 for AHB5 - #961
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HPRE5 value 0b101 divides by 3 per RM0493, which put HCLK5 at 33.3 MHz with a 100 MHz SYSCLK, above the 32 MHz AHB5 limit. Use 0b110 (divide-by-4) for 25 MHz.
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🟢 Approval recommended
No active review issues are reported for the AHB5 prescaler and explanatory comment update.
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What changed in this PR
Corrects the STM32WBA55 Nucleo board’s AHB5 prescaler so a 100 MHz system clock produces a 25 MHz AHB5 clock, below the 32 MHz limit.
Changes:
- Changes HPRE5 from
5(divide-by-3) to6(divide-by-4). - Corrects the comment to identify
0b110as the divide-by-4 encoding.
| File | Description |
|---|---|
hal/boards/stm32wba55cg_nucleo/wolfHAL_board.c |
Corrects the AHB5 prescaler value and its explanatory comment. |
Review effort: Balanced
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HPRE5 value 0b101 divides by 3 per RM0493, which put HCLK5 at 33.3 MHz with a 100 MHz SYSCLK, above the 32 MHz AHB5 limit. Use 0b110 (divide-by-4) for 25 MHz.